1. Field of the Invention
The present invention relates to an output circuit of a semiconductor device, and more particularly, to an open drain type output circuit in which a drain of a field effect transistor (FET) or the like is connected to an output terminal.
2. Description of the Background Art
FIG. 11 is a circuit diagram showing an example of an open drain type MOS driver circuit disclosed in the U.S. Pat. No. 5,023,488. In FIG. 11, an input signal is applied to a gate of a p-channel MOS transistor 1 as well as a gate of an n-channel MOS transistor 2. A voltage V.sub.TT is applied to a source of p-channel MOS transistor 1, and a drain thereof is connected to a drain of n-channel MOS transistor 2 and a node N1. A source of n-channel MOS transistor 2 is grounded, and node N1 is connected to an input of an inverter 3, a gate of an output transistor 7, and a source of an n-channel MOS transistor 5. An output of inverter 3 is applied to an inverter 4, and an output thereof is connected to a gate of an n-channel MOS transistor 6. A source of n-channel MOS transistor 6 is connected to a drain of n-channel MOS transistor 5, and the input signal is applied to a gate of n-channel MOS transistor 5. A drain of output transistor 7 as well as a drain of n-channel MOS transistor 6 are connected to an output pad 8. A load 10 is connected to output pad 8 through a cable 9.
The n-channel MOS transistor 2 shown in FIG. 11 is constituted by a transistor having large on resistance, i.e., small driving force in order to control so-called slew rate. This is for the purpose of reducing a noise element such as ringing caused by a parasitic inductance or capacitance which occurs when a state of output transistor 7 changes from on to off and an output voltage thereof rises from an "L" level to an "H" level.
FIG. 12 is a timing chart illustrating an operation of the driver circuit shown in FIG. 11, and FIGS. 13-15 show an operation condition of the output transistor.
The operation of the driver circuit shown in FIG. 11 will now be described with reference to FIG. 12. When an input signal rises from an "L" level to an "H" level as shown in FIG. 12(a), n-channel MOS transistor 2 is turned on, and therefore, potential of node N1 falls gradually as shown in FIG. 12(b), and the gate of output transistor 7 is discharged by n-channel MOS transistor 2. However, since the driving force of n-channel MOS transistor 2 is small, discharging speed does not increase. In addition, although n-channel MOS transistor 5 is turned on by the input signal as shown in FIG. 12(d), n-channel MOS transistor 6 is also turned on only for 1 nsec which is required for a signal of node N1 to pass through inverters 3 and 4 as shown in FIG. 12(e). At this time, a condition of output transistor 7 is equivalent to that in which an on resistance R1 of an inverter constituted by p-channel MOS transistor 1 and n-channel MOS transistor 2 in the preceding stage of node N1 is connected between the gate of output transistor 7 and the ground, and a resistance R2 with on resistances of n-channel MOS transistors 5 and 6 connected in series is connected between the gate and the drain of output transistor 7 as shown in FIG. 13(a), and since on resistance R1 is extremely large, output transistor 7 can be represented by an equivalent circuit as shown in FIG. 13(b). Thus, output transistor 7 is in a self-biasing condition, and a node voltage of output pad 8 drops relatively slowly towards a value of a threshold voltage of output transistor 7 plus .alpha.. As described above, a voltage of node N1 reduces gradually as shown in FIG. 12(b) for about 1 nsec during which both n-channel MOS transistors 5 and 6 are turned on as shown in FIG. 2(f).
Then, if n-channel MOS transistor 2 is turned on completely, output transistor 7 is turned off completely as shown in FIG. 12(g). Thus, output transistor 7 can be prevented from being turned off abruptly, resulting in reduction in noise.
In this case, as shown in FIG. 14, the swing at node N1 has a significant difference between rise and fall, and therefore, an output signal would have a short "H" level period and a long "H" level period even if an input signal has a duty cycle of a 50% "H" level period and a 50% "L" level period. In other words, the duty cycle cannot be maintained. This occurs even if the slew rate is not controlled in node N1, and as shown in FIG. 15, since a threshold voltage V.sub.T of n-channel MOS transistor 2 is lower than Vdd/2, t.sub.d1 becomes nearly equal to t.sub.d2 even if a rise time and a fall time of node N1 are the same, and the imbalance of the duty cycle is not eliminated.
FIG. 16 shows another example of a conventional output circuit. In this output circuit shown in FIG. 16, control of the slew rate is carried out at the time of transition of a state of an output transistor 13 from on to off.
In FIG. 16, an input signal is inverted by an inverter 3, and input to an inverter 4 and a gate of an n-channel MOS transistor 14 through a node N3. An output of inverter 4 is applied to respective gates of a p-channel MOS transistor 11, an n-channel MOS transistor 12 and an n-channel MOS transistor 15. The slew rate is controlled in p-channel MOS transistor 11 and n-channel MOS transistor 12 as in the case of p-channel MOS transistor 1 and n-channel MOS transistor 2 of FIG. 11. A power supply voltage Vdd is applied to a source of p-channel MOS transistor 11, and a drain thereof is connected to a drain of n-channel MOS transistor 12, a node N6, and a gate of output transistor 13. A source of output transistor 13 is grounded, and a signal is extracted from a drain thereof. Respective drains of n-channel MOS transistors 14 and 15 are connected to a source of n-channel MOS transistor 12 through a node N5, and respective sources of n-channel MOS transistors 14 and 15 are grounded.
FIG. 17 is a timing chart simulating an operation of the output circuit shown in FIG. 16. The operation of the output circuit shown in FIG. 16 will now be described with reference to FIG. 17. When an input signal rises from an "L" level to an "H" level as shown in FIG. 17(a), the input signal is inverted by inverter 3 and output to node N3, and node N3 falls to an "L" level as shown in FIG. 17(b). Thus, n-channel MOS transistor 14 is turned off, the input signal is further inverted by inverter 4, and node N4 attains to an "H" level as shown in FIG. 17(c). Accordingly, although n-channel MOS transistor 15 is turned on, node N5 falls from an "H" level to an "L" level gradually as shown in FIG. 17(d) due to small driving force of n-channel MOS transistor 12. Thus, node N6 falls gradually as shown in FIG. 17(e), and the drain of output transistor 13 rises gradually as shown in FIG. 17(f). Therefore, even if an input signal has the duty cycle of 50%, an output signal has the duty cycle of about 25% for an "H" level and about 75% for an "L" level, with a non-return-to-zero (RZ) waveform of 200 MHz. As a result, as frequency of the input signal becomes higher, the duty cycle of the output signal becomes less satisfactory.